Phased locked loop circuits (PLLs) are typically used whenever a periodic signal is to be generated whose frequency is an accurate multiple of the frequency of a very stable and low noise reference signal. A PLL is also used where the phase of an output signal has to track the phase of the reference signal. Applications include the generation of local oscillator signals in radio receivers are transmitters, as well as in clock recovery of digital communication systems.
The PLL is a closed loop feedback control system that continuously tries to reduce the error between the frequency or phase of its output signal and that of the reference. A typical PLL has what is referred to as a loop filter that connects a phase detector to a voltage controlled oscillator (VCO). The phase detector responds to the phase error between the reference and a feedback signal derived from the output, by making adjustments to a voltage signal in proportion to the phase error. Rather than directly applying the voltage signal to the input of the VCO, however, the signal is conditioned by the filter to produce the control voltage that adjusts the output frequency of the VCO. The filter is designed to help maintain the control loop stable, so that the loop does not enter an oscillatory condition. The filter may be viewed as smoothing out the input voltage to the VCO. The input voltage to the VCO adjusts the output frequency until a, for example, reference clock edge and a feedback clock edge are aligned.
In certain types of PLLs, stabilization using the loop filter is typically achieved by including a resistor in series with a capacitor, which together are in parallel with the output of the phase detector. Circuit designers have been faced with the challenge of reducing the size of such a PLL, particularly where it is implemented by advanced, small feature size integrated circuit manufacturing techniques.